Low-power Multi-Threshold CMOS (MTCMOS) FPGA Chip Utilizing Fine-Grained Leakage Management

This 0.13µm, dual VT test chip uses MTCMOS-style logic to implement a low-power FPGA architecture. The FPGA circuits reduce standby leakage by over 8× while holding their state. Idle sub-blocks in the design automatically enter sleep mode at a fine granularity, reducing active off-current by up to several times.