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This work presents a dual-factor authentication protocol and its low-power implementation for security of implantable medical devices (IMDs). The protocol incorporates traditional cryptographic first-factor authentication using Datagram Transport Layer Security - Pre-Shared Key (DTLS-PSK) followed by the user's touch-based voluntary second-factor authentication for enhanced security. With a low-power compact always-on wake-up timer and touch-based wake-up circuitry, our test chip consumes only 735 pW idle state power at 20.15 Hz and 2.5 V. The hardware accelerated dual-factor authentication unit consumes 8 μW at 660 kHz and 0.87 V. Our test chip was coupled with commercial Bluetooth Low Energy (BLE) transceiver, DC-DC converter, touch sensor and coin cell battery to demonstrate standalone implantable operation and also tested using in-vitro measurement setup.

This work presents a neural-network-based SAR ADC power side-channel attack (PSA) method and a 12-bit, 1.25MS/s secure SAR ADC whose current equalizers protect the ADC from PSA. A prototype SAR ADC was fabricated in 65nm CMOS to demonstrate the proposed concepts. Without PSA protection, the proposed PSA method decoded the power supply current waveforms of the prototype ADC into the corresponding A/D converter output bits with >99% bit-wise accuracy except for the LSB. With PSA protection, the prototype ADC demonstrated high resistance to the proposed PSA method, showing significant drop in bit-wise accuracy.

This work presents a neural-network-based SAR ADC power side-channel attack (PSA) method and a 12-bit, 1.25MS/s secure SAR ADC whose current equalizers protect the ADC from PSA. A prototype SAR ADC was fabricated in 65nm CMOS to demonstrate the proposed concepts. Without PSA protection, the proposed PSA method decoded the power supply current waveforms of the prototype ADC into the corresponding A/D converter output bits with >99% bit-wise accuracy except for the LSB. With PSA protection, the prototype ADC demonstrated high resistance to the proposed PSA method, showing significant drop in bit-wise accuracy.

Energy-autonomous wireless tags have been adopted in authentication and supply-chain management. At present, their size and cost, limited by packaging, prevent the tagging for small or inexpensive industrial/medical components. At the same time, pervasive electronic tagging raises serious privacy concerns related to inadvertent and malicious tracking of the tagged assets. In order to enable secure and ubiquitous asset tagging, fully passive particle-sized cryptographic chips without external packaging are highly desired. Recent prototypes that aim to address this challenge face either size, energy, communication, or security limitations. In this work, we present a package-less, monolithic tag chip with built-in photovoltaic powering and a compact elliptic-curve-cryptography (ECC) processor. Using far-field backscatter communication at 260GHz, the CMOS tag, while integrating a 2×2 antenna array with beam-steering capability, has a size of only 1.6mm2.

Energy-autonomous wireless tags have been adopted in authentication and supply-chain management. At present, their size and cost, limited by packaging, prevent the tagging for small or inexpensive industrial/medical components. At the same time, pervasive electronic tagging raises serious privacy concerns related to inadvertent and malicious tracking of the tagged assets. In order to enable secure and ubiquitous asset tagging, fully passive particle-sized cryptographic chips without external packaging are highly desired. Recent prototypes that aim to address this challenge face either size, energy, communication, or security limitations. In this work, we present a package-less, monolithic tag chip with built-in photovoltaic powering and a compact elliptic-curve-cryptography (ECC) processor. Using far-field backscatter communication at 260GHz, the CMOS tag, while integrating a 2×2 antenna array with beam-steering capability, has a size of only 1.6mm2.