A 0.36V Energy-Efficient 128Kb 6T SRAM With Output Data Prediction In 28nm FDSOI

The aggressive scaling of SRAM bit-cell size with every technology node makes it extremely challenging to reduce the Vdd,min of SRAMs, due to the increasing effect of device variations. However, Vdd scaling is crucial in reducing the energy consumption of SRAMs, which is a significant portion of the overall energy consumption in modern micro-processors. Energy savings in SRAM are particularly important for battery-operated applications, which run from a very constrained power-budget. This work presents a low-voltage, energy-efficient SRAM designed in a 28nm fully depleted SOI (FDSOI) technology. The SRAM achieves a minimum Vdd of 0.36V, while still having the area advantage by using 6T bit-cells. Dynamic forward body-biasing is used to improve the Vdd,min. Improved array layout helps in reducing the switching energy. An average energy/bit-access of 52.5fJ has been achieved at 0.45V. Furthermore, by implementing data prediction in the read-path, up to 36% dynamic energy savings are obtained.