A 256kb 65nm 8T Sub-Threshold SRAM Employing Sense-Amplifier Redundancy

An 8T SRAM achieves full read and write functionality at 350mV. The read-buffered bit-cell eliminates the read static noise margin limitation; peripheral control of the read-buffer eliminates sub-Vt bit-line leakage from unaccessed cells; peripheral control of the bit-cell supply voltage ensures write-abilty in the presence of variation; and the technique of sense-amplifier redundancy improves the area-offset tradeoff in the sensing network by over a factor of 5.