A 28nm High-Density 6T SRAM With Optimized Peripheral Assist

A 128kb SRAM macro employing a 0.12µm2 6T high-density bit-cell is fabricated in a low-power 28nm CMOS process. Hierarchical bit-line architecture, signal boosting and pre-read during write schemes enable operation down to 0.6V while introducing minimum area overhead. Performance of the memory scales from 20 to 400MHz on 0.6 to 1V operating voltage range where active power consumption scales from 2.8 to 68.5mW.