A 6-bit, 0.2V To 0.9V Highly Digital Flash ADC With Comparator Redundancy

A 6-bit highly digital flash ADC is implemented in a 0.18µm CMOS process. The ADC operates in the subthreshold regime down to 200mV and employs comparator redundancy to improve linearity. Common-mode rejection is implemented digitally via an IIR filter. The ADC's minimum FOM is at a supply of 0.4V, where it achieves a FOM of 125fJ/conversion-step and a ENOB of 5.05 at 400kSPS.