A 6mW, 5,000-Word Real-Time Speech Recognizer Using WFST Models

This 2.5 x 2.5 mm, 65 nm test chip is a speech decoder that can be programmed with industry-standard WFST and GMM models. Algorithm and architectural enhancements were incorporated in order to achieve real-time performance with limited internal memory size and external memory bandwidth. The chip performs a 5,000 word recognition task in real-time with 13.0% word error rate, 6.0 mW core power consumption, and a search efficiency of approximately 16 nJ per hypothesis.