HEVC Video Decoder For 4K Ultra HD Applications

A video decoder chip supporting the High Efficiency Video Coding (HEVC) standard is designed in 40nm CMOS. The chip runs at 200 MHz at 0.9V with a throughput of 249 Mpixel/s to meet the requirements of 4K Ultra HD applications. Various architectural innovations are implemented in the chip to address large and variable pixel block sizes in HEVC and longer interpolation filters compared to the previous H.264/AVC standard. A motion compensation cache is designed to reduce the average bandwidth required from external memory by 67%. The chip consumes 78mW when decoding video at a resolution of 3840x2160 at 30 frames/s. The total system efficiency including simulated DRAM power is 1.19 nJ/pixel.