Ultra Low Power ADC For Wireless Micro-Sensors

A rate scalable (0-200kS/s) and resolution scalable (8b or 12b) ADC is implemented using the successive approximation architecture. At the highest performance point (12b, 100kS/s) it consumes just 25µW, and the power decreases linearly with reduced sampling rate. Efficient operation is obtained through several techniques: Analog offset compensation in the latch improves the comparator power-delay product; robust self timing eases the settling time requirements; and switched-capacitor auto-zero reference generation maximizes common-mode rejection.