Voltage Scaling In SRAM

There is a need for large embedded memory that operates over a wide range of supply voltage compatible with the limits of static CMOS logic. This chip demonstrates circuit solutions to voltage scaling in SRAM for both active operation and standby mode in an 8T SRAM fabricated in 45 nm SOI CMOS. The chip exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global bitline scheme. Finally, a data retention voltage sensor has been developed to predict the mismatch-limited minimum standby voltage without corrupting the contents of the memory.