A 55.8-to-64.2GHz, 58.3fsrms-Jitter, -250.2dB-FoMJ Fractional-N Cascaded PLL In 28nm CMOS

J. Jung, E. Lee, D. Han, J. Wang, A. P. Chandrakasan, and R. Han, “A 55.8-to-64.2GHz, 58.3fsrms-Jitter, -250.2dB-FoMJ Fractional-N Cascaded PLL in 28nm CMOS,” 2025 IEEE Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan, (June 2025).