A Low-Power DCT Core Using Adaptive Bitwidth And Arithmetic Activity Exploiting Signal Correlations And Quantization

Xanthopoulos, T., A. P. Chandrakasan, "A Low-Power DCT Core Using Adaptive Bitwidth and Arithmetic Activity Exploiting Signal Correlations and Quantization," IEEE Symposium on VLSI Circuits, pp. 11-12, Kyoto, Japan, June 1999.