A Methodology For Modeling The Effects Of Systematic Within-Die Interconnect And Device Variation On Circuit Performance

Mehrotra, V., S. Sam, D. Boning, A. P. Chandrakasan, R. Vallishayee, S. Nassif, "A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance," IEEE/ACM Design Automation Conference, pp. 172-175, Los Angeles, California, June 2000.