Design And Analysis Of A Hardware-Efficient Compressed Sensing Architecture For Data Compression In Wireless Sensors

Chen, F., A. P. Chandrakasan, V. M. Stojanovic, "Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors, " IEEE Journal of Solid-State Circuits, vol.47, no.3, pp.744-756, March 2012.