Full-Chip Sub-Threshold Leakage Power Prediction Model For Sub-0.18 Um CMOS

Narendra, S., V. De, S. Borkar, D. Antoniadis, and A. P. Chandrakasan, "Full-Chip Sub-Threshold Leakage Power Prediction Model for sub-0.18 um CMOS," IEEE International Symposium on Electronics and Design, pp. 19-23, Monterey, California, pp.19-23, August 2002.