Full-Chip Subthreshold Leakage Power Prediction And Reduction Techniques For Sub-0.18um CMOS

Narendra, S., V. De, S. Borkar, D. Antoniadis, A. P. Chandrakasan, "Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18um CMOS," IEEE Journal Of Solid-State Circuits, pp. 501-510, March 2004.