Conferences – Page 2 – Energy-Efficient Circuits and Systems Group

MEGA. mini: A Universal Generative AI Processor with a New Big/Little Core Architecture for NPU

D. Han and A. P. Chandrakasan, "MEGA.mini: A Universal Generative AI Processor with a New Big/Little Core Architecture for NPU," 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA (Feb 2025)

A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator

A. G. Amer, M. Ashok, X. Zhang, J. Cohn and A. P. Chandrakasan, "A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator," 2025 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), Bangalore, India (Jan 2025)

A 0.75mm(2) 407μW Real-Time Speech Audio Denoiser with Quantized Cascaded Redundant Convolutional Encoder-Decoder for Wearable IoT Devices

Kochar, D.V., Ashok M., Chandrakasan A.P., "A 0.75 mm 2 407μW Real-Time Speech Audio Denoiser with Quantized Cascaded Redundant Convolutional Encoder-Decoder for Wearable IoT Devices." 2025 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID). IEEE (Jan 2025)

Reconfigurable 3D Edge Sensing System of Carbon Nanotube Sensing and Silicon CMOS from a Commercial Manufacturing Facilities

A. G. Amer, G. Hills, G. Kyriazidis, A. P. Chandrakasan and M. M. Shulaker, "Reconfigurable 3D Edge Sensing System of Carbon Nanotube Sensing and Silicon CMOS from a Commercial Manufacturing Facilities," 2024 IEEE Workshop on Signal Processing Systems (SiPS) (November 2024)

A Robust BLE-compatible Wake-up Receiver for Ingestible Device with In-vivo Evaluation

S. Shin, Y. Jeno, I. Ballinger, M.I.W. Khan, A. Pettinari, A.M. Hayward, "A Robust BLE-compatible Wake-up Receiver for Ingestible Device with In-vivo Evaluation," 2024 46th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (Jul 2024)

HEAP: A Fully Homomorphic Encryption Accelerator with Parallelized Bootstrapping

R. Agrawal, A. Chandrakasan and A. Joshi, "HEAP: A Fully Homomorphic Encryption Accelerator with Parallelized Bootstrapping," 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Buenos Aires, Argentina, (June 2024)

A Secure Digital In-Memory Compute Macro with Protections Against Side-Channel and Bus Probing Attacks

M. Ashok, S. Maji, X. Zhang, J. Cohn, A.P. Chandrakasan, ”A Secure Digital In-Memory Compute Macro with Protections Against Side-Channel and Bus Probing Attacks,” IEEE Custom Integrated Circuits Conference (CICC), Apr. 2024

A 0.7cm2 3.5GHz, -31 dBm sensitivity batteryless 5G energy harvester backscattering chip for asset identification in IoT-enabled warehouses

D.U. Yildirim, J. Jung, A. Elsakka, G. Moschetti, M. Lopez, J. Hansryd, T. Palacios and A. P. Chandrakasan, "A 0.7cm2 3.5GHz, -31 dBm sensitivity batteryless 5G energy harvester backscattering chip for asset identification in IoT-enabled warehouses" IEEE Custom Integrated Circuit Conference (CICC), Apr. 2024

12.5 A Packageless Anti-Tampering Tag Utilizing Unclonable Sub-THz Wave Scattering at the Chip-Item Interface

E. Lee, X. Chen, M. Ashok, J. Won, A. Chandrakasan and R. Han, "12.5 A Packageless Anti-Tampering Tag Utilizing Unclonable Sub-THz Wave Scattering at the Chip-Item Interface," 2024 IEEE International Solid-State Circuits Conference (ISSCC), Feb 2024.

Mad: Memory-aware design techniques for accelerating fully homomorphic encryption

R. Agrawal, L.D. Castro, C. Juvekar, A. Chandrakasan, V. Vaikuntanathan, A. Joshi, "MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption", 56th IEEE/ACM International Symposium on Microarchitecture (MICRO '23), Dec 2023.