Journals & Magazines – Energy-Efficient Circuits and Systems Group

A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving -250.2dB FoMJ in 28-nm CMOS

J. Jung, E. Lee, D. Han, J. Wang, A. P. Chandrakasan, and R. Han, “A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving -250.2dB FoMJ in 28-nm CMOS,” 2026 IEEE Journal of Solid-State Circuits (Feb 2026).

The potential of miniaturized ingestible electronics

G. Traverso, P. Sheehan, A. Bahai, R. Langer, A.P. Chandrakasan, “The potential of miniaturized ingestible electronics”, Nat Electronics 9, 5–7 (Jan 2026)

Real-Time 3D Ultrasound Imaging with an Ultra-Sparse, Low Power Architecture

C. Marcus, M. O. G. Nayeem, A. Shah, J. Hou, S. Viswanath, M. Eusebio, D. Sadat, A. P. Chandrakasan, T. Ozmen, C. Dagdeviren, “ Real-Time 3D Ultrasound Imaging with an Ultra-Sparse, Low Power Architecture.” Advanced Healthcare Materials (Jan 2026)

Heterogeneously Integrated Nitrogen-Vacancy Sensing for Real-Time CMOS Security Threat Detection

M. Ashok,Y. Hu, H. Wang, E.G. Arnault, H.Raniwala, A.G. Amer, M. Trusheim, D.R. Englund, A.P. Chandrakasan, " Heterogeneously Integrated Nitrogen-Vacancy Sensing for Real-Time CMOS Security Threat Detection," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Nov. 2025)

MEGA.mini: An Energy-Efficient NPU Leveraging a Novel Big/Little Core With Hybrid Input Activation for Generative AI Acceleration

D. Han, A. P. Chandrakasan, "MEGA.mini: An Energy-Efficient NPU Leveraging a Novel Big/Little Core With Hybrid Input Activation for Generative AI Acceleration," in IEEE Journal of Solid-State Circuits (November 2025)

Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement With Minimal Data Input

D. V. Kochar, M. Ashok, J. Cohn, X. Zhang and A. P. Chandrakasan, "Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement With Minimal Data Input," in IEEE Transactions on Circuits and Systems I: Regular Papers (Aug 2025)

Blog Archives

A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving -250.2dB FoMJ in 28-nm CMOS

The potential of miniaturized ingestible electronics

Real-Time 3D Ultrasound Imaging with an Ultra-Sparse, Low Power Architecture

Heterogeneously Integrated Nitrogen-Vacancy Sensing for Real-Time CMOS Security Threat Detection

MEGA.mini: An Energy-Efficient NPU Leveraging a Novel Big/Little Core With Hybrid Input Activation for Generative AI Acceleration

Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement With Minimal Data Input

Protecting the Mixed-Signal Domain: Secure ADCs for Internet of Things Devices

Digital In-Memory Compute for Machine Learning Applications With Input and Model Security

Secure Machine Learning Hardware: Challenges and Progress

A Fully-Integrated Energy-Scalable Transformer Accelerator for Language Understanding on Edge Devices