Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning
Wang M., A. P. Chandrakasan, "Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2019.
Blog Archives
Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols
Banerjee U., T. S. Ukyab, A. P. Chandrakasan, "Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols," IACR Conference on Cryptographic Hardware and Embedded Systems (CHES), Aug. 2019.
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications
Banerjee U., A. Wright, C. Juvekar, M. Waller, Arvind, A. P. Chandrakasan, "An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications," IEEE Journal of Solid-State Circuits, vol. 54, no. 8, pp.2339-2352, Aug. 2019.
Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols
Banerjee U., T. S. Ukyab, A. P. Chandrakasan, "Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols," IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2019, no. 4, pp.17-61, Aug. 2019.
Modern microprocessor built from complementary carbon nanotube transistors
Hills G., C. Lau, A. Wright, S. Fuller, M. D. Bishop, T. Srimani, P. Kanhaiya, R. Ho, A. Amer, Y. Stein, D. Murphy, Arvind, A. P. Chandrakasan, M. M. Shulaker, "Modern microprocessor built from complementary carbon nanotube transistors," Nature, vol. 572, no. 7771, pp.595-602, Aug. 2019.
Strain-Programmable Fiber-based Artificial Muscle
Kanik M., S. Orguc, G. Varnavides, J. Kim, T. Benavides, D. Gonzalez, T. Akintilo, C. C. Tasan, A. P. Chandrakasan, Y. Fink, P. Anikeeva, "Strain-Programmable Fiber-based Artificial Muscle," Science, vol. 365, no. 6449, pp.145-150, Jul. 2019.
SHARC: Self-Healing Analog with RRAM and CNFETs
Amer A. G., R. Ho, G. Hills, A. P. Chandrakasan, M. M. Shulaker, "SHARC: Self-Healing Analog with RRAM and CNFETs," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019.
An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things
Banerjee U., A. Pathak, A. P. Chandrakasan, "An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019.
CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks
Biswas A., A. P. Chandrakasan, "CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks," IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp.217-230, Jan. 2019.