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6.5GHz CMOS Frequency Synthesizer with FSK Modulator

Image of chip design
This chip will enable energy-efficient communication for low-power wireless sensor networks. Fabricated in 0.25µm BiCMOS process, the modular achieves 20µs start-up time with 2.5 Mbps data rate while consuming 22mW, where 18mW is consumed in the VCO and 4mW is consumed in the PLL.