This chip explores the design of a low-power digital processor for wireless network sensor nodes, employing techniques such as hardwired algorithms, lowered supply voltages, and subsystem clock gating.
A rate scalable (0-200kS/s) and resolution scalable (8b or 12b) ADC is implemented using the successive approximation architecture. At the highest performance point (12b, 100kS/s) it consumes just 25µW, and the power decreases linearly with reduced sampling rate. Efficient operation is obtained through several techniques: Analog offset compensation in the latch improves the comparator power-delay product; robust self timing eases the settling time requirements; and switched-capacitor auto-zero reference generation maximizes common-mode rejection.
Two analog-to-digital converters are integrated on this 0.18µm CMOS chip to provide Nyquist sampling of quadrature UWB signals that have been down-converted to baseband. The ADCs use a six-way time-interleaved successive approximation register topoogy to achieve a total 15.6mW core power consumption from a 1.8V digital and 1.2V analog; the resolution is scalable down to 1-bit for further power savings.
This chip is the RF front-end for a 100Mb/s pulsed ultra-wideband (UWB) transceiver that communicates in 14 channels spaced 528 MHz apart in the 3.1-10.6 GHz band. It features an FCC compliant BPSK pulse-shaping transmitter, a direct-conversion receiver with 802.11a notch filtering, and two cross-coupled quadrature VCOs. The chip was fabricated in a 0.18µm SiGe BiCMOS process.
