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A prototype of a pre-standard algorithm developed for HEVC called Massively Parallel CABAC that addresses a key bottleneck in the video decoder is implemented in a 65-nm CMOS process. The scalable testchip achieves a throughput of 24.11bins/cycle, which enables it to decode the max H.264/AVC bitrate (300Mb/s) with a 18MHz clock at 0.7V, consuming 12.3pJ/bin. At 1.0V, it decodes a peak of 3026Mbins/s for a bit-rate of 2.3Gb/s, which is enough for over seven 300Mb/s sequences or a 4kx2k resolution video at 186 fps. Joint algorithm and architecture optimizations are used to reduce critical path delay and memory requirements with little or no cost in coding efficiency.

The DC-DC converter is designed in a 45nm digital CMOS process and is capable of handling 2.8 to 4.2V battery. The main converter is a buck regulator with efficiency of 75% to 87% over a wide load range (10µA to 100mA). It utilizes switched capacitor converters for internal rail generation and has a IC-DAC DPWM.

This chip is intended as a processor on a wearable medical monitoring sensor node, which continuously analyzes a subject's vital signs. In addition to a 16-bit general-purpose CPU, the chip leverages custom hardware accelerators to reduce the energy needed for common signal processing in biomedical applications. Voltage scaling and module-level power gating allow the chip to adapt to different applications with varied performance/processing demands. While running two published EEG and EKG analysis applications, the processor achieved > 10× energy reduction compared to a general-purpose low power CPU.

A compact, low-power, digitally-assisted sensor interface for biomedical applications is implemented in a 0.18µm CMOS process. It exploits oversampling and digital design to reduce system area and power, while making the system more robust to interferers. Anti-aliasing is achieved using a charge-sampling filter with a sinc frequency response and programmable gain. A mixed-signal feedback loop creates a sharp, programmable notch for interference cancelation. The on-chip blocks operate from a 1.5V supply and consume between 255nW and 2.5µW depending on noise and bandwidth requirements.

A 128kb SRAM macro employing a 0.12µm2 6T high-density bit-cell is fabricated in a low-power 28nm CMOS process. Hierarchical bit-line architecture, signal boosting and pre-read during write schemes enable operation down to 0.6V while introducing minimum area overhead. Performance of the memory scales from 20 to 400MHz on 0.6 to 1V operating voltage range where active power consumption scales from 2.8 to 68.5mW.