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This 2.5 x 2.5 mm, 65 nm test chip is a speech decoder that can be programmed with industry-standard WFST and GMM models. Algorithm and architectural enhancements were incorporated in order to achieve real-time performance with limited internal memory size and external memory bandwidth. The chip performs a 5,000 word recognition task in real-time with 13.0% word error rate, 6.0 mW core power consumption, and a search efficiency of approximately 16 nJ per hypothesis.

ADCs used in medical and industrial monitoring often transduce signals with short bursts of high activity followed by long idle periods. Examples include biopotential, sound, and accelerometer waveforms. Current approaches to save energy during periods of low signal activity include variable resolution and sample rate systems, asynchronous level-crossing ADCs, and ADCs that bypass bitcycles when the signal is within a predefined small window. This work presents a signal-activity-based power-saving algorithm called LSB-first successive approximation (SA) that maintains a constant sample rate and resolution, scales logarithmically with signal activity, and does not inherently suffer from slope overload.