Fast Algorithm for Clock Grid Simulation
Sotiriadis, P., O. Franza, D. Bailey, B. Calhoun, D. Lin, A. Chandrakasan, "Fast Algorithm for Clock Grid Simulation," IEEE ESSCIRC 2002, Florence, Italy, September 2002.
Blog Archives
Full-Chip Sub-Threshold Leakage Power Prediction Model for sub-0.18 um CMOS
Narendra, S., V. De, S. Borkar, D. Antoniadis, and A. P. Chandrakasan, "Full-Chip Sub-Threshold Leakage Power Prediction Model for sub-0.18 um CMOS," IEEE International Symposium on Electronics and Design, pp. 19-23, Monterey, California, pp.19-23, August 2002.
A Framework for Energy-Scalable Communication in High-Density Wireless Networks
Min, R., A. P. Chandrakasan, "A Framework for Energy-Scalable Communication in High-Density Wireless Networks," IEEE International Symposium on Electronics and Design, pp. 36-41, Monterey, California, August 2002.
Energy reduction and fundamental energy limits in digital VLSI circuits
Sotiriadis, P.P. V. Tarokh. A. Chandrakasan, "Energy reduction and fundamental energy limits in digital VLSI circuits," International Symposium on Information Theory, pp. 393, July 2002.
Bounding the Lifetime of Sensor Networks Via Optimal Role Assignments
Bhardwaj, M., A. P. Chandrakasan, "Bounding the Lifetime of Sensor Networks Via Optimal Role Assignments," IEEE Infocom, pp. 1587-1596, New York, June 2002. [PowerPoint]
A 6.5GHz CMOS FSK Modulator for Wireless Sensor Applications
Cho, S., A. P. Chandrakasan, "A 6.5GHz CMOS FSK Modulator for Wireless Sensor Applications," IEEE Symposium on VLSI Circuits, pp. 182-185, Honolulu, Hawaii, June 2002.
Maximum Achievable Energy Reduction Using Coding with Applications to Deep Sub-Micron Buses
Sotiriadis, P., A. P. Chandrakasan, V. Tarokh, "Maximum Achievable Energy Reduction Using Coding with Applications to Deep Sub-Micron Buses," IEEE ISCAS, pp. 85-88, Scottsdale, Arizona, May 2002.
Optimal Supply and Threshold Scaling for Sub-threshold CMOS circuits
Wang, A., Chandrakasan, A. P., S. Kosonocky, "Optimal Supply and Threshold Scaling for Sub-threshold CMOS circuits," IEEE Computer Society Annual Symposium on VLSI, pp. 5-9, Pittsburgh, Pennsylvania, April 2002.
Adaptive Body-bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor
Tschanz, J., J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. P. Chandrakasan, V. De, "Adaptive Body-bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor," IEEE ISSCC, 422-423, San Francisco, California, February 2002. [Supplement]
A 175mV Multiply-Accumulate Unit Using an Adaptive Supply Voltage Voltage and Body Bias (ASB) Architecture
Miyazaki, M. J. Kao, A. Chandrakasan, "A 175mV Multiply-Accumulate Unit Using an Adaptive Supply Voltage Voltage and Body Bias (ASB) Architecture," IEEE ISSCC, pp. 58-59, San Francisco, California, February 2002.