2012 – Page 2 – Energy-Efficient Circuits and Systems Group

A 12b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC

Lee, S., A. P. Chandrakasan, H.-S. Lee, "A 12b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC", IEEE Journal of Solid-State Circuits, vol.47, no.7, pp.1603-1614, July 2012.

A 0.6V 2.9μW Mixed-Signal Front-End for ECG Monitoring

Yip, M., J.L. Bohorquez, and A. P. Chandrakasan, "A 0.6V 2.9μW Mixed-Signal Front-End for ECG Monitoring," IEEE Symposium on VLSI Circuits (VLSIC), pp. 66-67, June 2012.

A 440pJ/bit 1Mb/s 2.4GHz Multi-Channel FBAR-based TX and an Integrated Pulse-shaping PA

Paidimarri, A., P. Nadeau, P. Mercier, A. Chandrakasan, "A 440pJ/bit 1Mb/s 2.4GHz Multi-Channel FBAR-based TX and an Integrated Pulse-shaping PA," IEEE Symposium on VLSI Circuits (VLSIC), pp.34-35, June 2012.

Multi-channel 180pJ/bit 2.4GHz FBAR-based Receiver

Nadeau, P., A. Paidimarri, P. Mercier, A. Chandrakasan, "Multi-channel 180pJ/bit 2.4GHz FBAR-based Receiver," IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 381-384, June 2012.

Approaching the Theoretical Limits of a Mesh NoC with a 16-Node Chip Prototype in 45nm SOI

Park, S., T. Krishna, C.-H. O. Chen, B. Daya, A. P. Chandrakasan, L.-S. Peh, "Approaching the Theoretical Limits of a Mesh NoC with a 16-Node Chip Prototype in 45nm SOI", Design Automation Conference (DAC), June 2012.

Self-aware Computing in the Angstrom Processor

Hoffmann, H., J. Holt, G. Kurian, E. Lau, M. Maggio, J. E. Miller, S. M. Neuman, M. Sinangil, Y. Sinangil, A. Agarwal, A. P. Chandrakasan, S. Devadas, "Self-aware Computing in the Angstrom Processor", Design Automation Conference (DAC), June 2012.

Technique for Efficient Evaluation of SRAM Timing Failure

Qazi, M., M. Tikekar, L. Dolecek, D. Shah, A. P. Chandrakasan, "Technique for Efficient Evaluation of SRAM Timing Failure," IEEE Transactions on Very Large Scale Integration Systems, accepted June 2012.

The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage

Rithe, R., S. Chou, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, A. Chandrakasan, "The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 20, No. 5, 911-924, May 2012.

Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors

Chen, F., A. P. Chandrakasan, V. M. Stojanovic, "Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors, " IEEE Journal of Solid-State Circuits, vol.47, no.3, pp.744-756, March 2012.

An 8-Channel Scalable EEG Acquisition SoC With Fully Integrated Patient-Specific Seizure Classification and Recording Processor

Yoo, J., L. Yan, D. El-Damak, M. Bin Altaf, A. Shoeb, H-J. Yoo, A. Chandrakasan, "An 8-Channel Scalable EEG Acquisition SoC With Fully Integrated Patient-Specific Seizure Classification and Recording Processor," IEEE International Solid-State Circuits Conference (ISSCC), Feb 2012.